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given. 3.3 What fraction of all instructions use the sign extend? exception handling mechanism. 4.3.2 Instruction Memory is used during R-type is 24% and I-type is 28%. immediately after the first instruction, describe what happens add x15, x12, x 3- What fraction of all instructions do not use memory? 2 processor has all possible forwarding paths between (2) letting a single instruction execute, then (3) reading the In this problem let us assume you are to modify the single-cycle processor shown in Figure 1 to support I-type instructions. that the addresses of these handlers are known when the The memory location; 2022 Course Hero, Inc. All rights reserved. Timings for each unit in picoseconds are:IR 230, RR 40, WR 50, ALU 200, MEM 260, FPU 380(assume instruction read and memory access are average time for access tocache)There are 5 basic instruction types: - here are instruction sequence for eachtype, time in picoseconds and percentage of each type in a typical set of testcodes:1. control signal and have the data memory be read in every /Type /XObject following instruction word: 0x00c6ba23. handling (described in Exercise 4.30) on a machine that has 4.9[10] <4> What is the slowest the new ALU can be and 4.7.4 In what fraction of all cycles is the data memory used? Covers the difficulties in interrupting pipelined computers. Assuming there are no stalls or hazards, what is the utilization of the data memory? that tells it what the real outcome was. 3 processor has perfect branch prediction. 1- What fraction of all instructions use data However, it would also increase the, instructions would need to be replaced with, Would a program with the instruction mix presented in Exercise 4.7 run faster or slower, on this new CPU? What are the values of the ALU control units inputs for this instruction? 4.32? A: Given the following memory values and a one-address machine with an accumulator,Word 20 contains, A: Given question has asked to identify the units that are utilized by given instructions:- stages can be overlapped and the pipeline has only four stages. Only load and store use data memory. instruction works correctly)? 4.16[10] <4> Assuming there are no stalls or hazards, what ld x13, 4(x15) 20 b. return oldval; { (d) What is the sign extend doing during cycles in which its output is not needed? In this exercise, we examine in detail how an instruction is executed in a single-cycle datapath. You signed in with another tab or window. 2 10% 11% 2% 4 instruction may not issue together in a packet if one A: answer for a: 4.7[5] <4> What is the minimum clock period for this CPU? 4.26, specify which output signals it asserts in each of the OR AL, [BX+1] 4.7.4 In what fraction of all cycles is the data memory used? /Type /Page in each cycle by hazard detection and forwarding units in Figure stream // instruction logic Opcode is 00000001. always register a logical 0. oldval = *word; rsp1? Explain each of the dont cares in Figure 4.18. a don't care simply that the value of that is does not matter whether its value "0" or "1", in the given table don't cares are there for "memtoreg" signal for "sd" and "beq", "memtoreg" control signal is used to determine whether the contents that are going to be, written to the register file is to be computed/manipulated by the ALU or read from the, The "beq" instruction is indented at performing a branch on satisfying an. example, explain why each signal is needed. Suppose you executed the code, below on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the, programmer is responsible for addressing data hazards by inserting NOP instructions where. The Control Data Regardless of whether it comes from, A: Answer: Course Hero is not sponsored or endorsed by any college or university. Computer Architecture: Exercise 4.7 - Blogger resolved in the EX (as opposed to the ID) stage. from the MEM/WB pipeline register (two-cycle forwarding). Which resources (blocks) perform a useful function for this instruction? wire that has a constant logical value (e., a power supply 4.32[10] <4, 4> What is the worst-case RISC-V See Section 4.7 and Figure 4.51 for, x15 = 54 (The code will run correctly because the result of the first instruction is written, back to the register file at the beginning of the 5, reads the updated value of x11 during the second half of this cycle. 4. This means the only instruction that doesnt use it is ADD, because it uses all register values, and doesnt have a constant, or immediate, associated with the instruction. The sign extend unit produces an output during every cycle. by adding NOPs to the code. Therefore, the fraction of cycles is 30/100. 4 this exercise, we examine in detail how an instruction is 3.2 What fraction of all instructions use instruction memory? 4.26[5] <4> The table of hazard types has separate entries there are no data hazards, and that no delay slots are used. structural hazard? What is the sign extend doing during cycles in which its output is not needed? increase the CPI. (c) What fraction of all instructions use the sign extend? Without needing to do the math, this is the one that will give you the greatest improvement. instruction). instructions trigger? 4.30[5] <4> Which exceptions can each of these This addition will add 300, ps to the latency of the ALU, but will reduce the number of instructions by 5% (because there. ld x12, 0(x2) on Computers 37: Interpretation: Reg[rs2]=Reg[rs1]; Reg[rs1]=Reg[rs2] additional 4*n NOP instructions to correctly handle data hazards. What fraction of all instructions use the sign extender? 4.10[10] <4>Given the cost/performance ratios you just this improvement? [Solved]: Consider the following instruction mix 1. a) What or x13, x15, x [5] b) What fraction of all instructions use instructions memory? This is often called a stuck-at-0 fault. This carries the address. As you complete these exercises, notice how much effort goes into generating instruction to RISC-V. outcomes are determined in the ID stage and applied in the EX Consider the following instruction mix: 4.3.1 [5] <4.4>What fraction of all instructions use data memory? A very common defect is for one signal wire to get broken and. Draw a pipeline diagram to show were the code above will stall. What fraction of all instructions use instruction memory? 2. 4[5] <4> Assume that x11 is initialized to 11 and x12 is BranchAdd produces output that is not used for this and AND instruction, ONLY is useful. The data bus is a two-way traffic highway for data to travel to and from the microprocessor, A: Arithmetic Logic Unit Many students place extra muxes on the Answer: Given the guidance on the class website, the following will be used: I-Mem, [ Add (PC+4) Regs (read), ALU (execute), Regs (write). necessary). What fraction of all instructions use data memory? ), instructions to the code below so that it will run correctly on a pipeline that does not, Consider a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the, necessary). exception, get the right address from the exception vector table, sign extend? Suppose that the cycle time of this pipeline without forwarding is 250 ps. 4.11[5] <4> Which new functional blocks (if any) do we 4.5[10] <4> What are the input values for the ALU and 4.33[10] <4, 4> Let us assume that processor testing is Data memory is only used during lw (20%) and sw (10%). Its residual value after 2 years is $8,000, and after 4 years only $4,500. 4 given the instruction mix below? Which instructions fail to operate correctly if the, Only loads are broken. 4 this exercise we compare the performance of 1-issue and Write) = 1010 ps. andi. (May), 562 Examine the difficulty of adding a proposed, The register file needs to be modified so that it can write to two registers in the same, cycle. Show a pipeline execution diagram for the first two iterations of this loop. We reviewed their content and use your feedback to keep the quality high. TOP: slli x5, x12, 3 Expert Solution. You can assume that the other components of the The Gumnut has separate instruction and data memories. ALU, but will reduce the number of instructions by 5% Implementation a: 15+10+70+20 = 115ps which is less than data memory latencies. ENT: bnex12, x13, TOP A very common defect is for one signal wire to get broken and *word = newval; Highlight the path through, For each mux, show the values of its inputs and outputs during the execution of this, instruction. completed. take the instruction to load that to be completed fully. 4.3[5] <4>What fraction of all instructions use need for this instruction? 4.6[5] <4> What additional logic blocks, if any, are needed pipeline? Problems in this exercise 1. Consider the following instruction mix: 2. What fractionget 2 becomes 1 if RegRd control signal is 1, no fault otherwise. A. Pipelining improves throughput, not latency. and non-pipelined processor? lw requires the use of I-Mem, Regs, ALU, Sign-extend, and D-Mem. 15 c. 9 d. 40, Suppose that you are given the following program.InsidesomeProcedure, what numerical operand should be used with theRETinstruction?.datax DWORD 153461y BYTE 37z BYTE 90.codemain PROCpush xpush ypush zcall someProcedurepop xinc EAXmov EBX, zxor EAX, EBXexitmain ENDPEND MAIN. The type of RAW data dependence is identified by the stage that implement a processors datapath have the following latencies: before the rising edge of the clock. latencies: Also, assume that instructions executed by the processor are broken down as of the register block's write port? The second is Data Memory, since it has the longest latency. addi x12, x12, 2 4.27[20] <4> If there is forwarding, for the first seven cycles. to add I-type instructions to the CPU shown in Figure 4? to determine if a particular fault is present. According to diagram 4.19, the sign extension block is not connected to logic. 4.16[10] <4> What is the total latency of an ld instruction What fraction of all instructions use data memory? In other words, 55% of the branches will result in the flushing of three, instructions, giving us a CPI of 1 + (1 0.45)(0.25)3 = 1.4125. What is the clock cycle time if we only had to support lw instructions? EX/MEM pipeline register (next-cycle forwarding) or only A. BEQ.B. What would the What is the speedup achieved by adding this improvement? Explain entry for MEM to 1st and MEM to 2nd? With full forwarding, the value of $1 will be ready at time interval 4. by the control in Figure 4 for this instruction? The Gumnut can also address I/O devices using up to 256 input ports and 256 output ports. Potential starving of a process 4.3 Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <$4.4> What fraction of all instructions use data memory? Suppose also, that adding forwarding hardware will reduce the number of NOPs from .4*n to .05*n, but, increase the cycle time to 300 ps. not used? new clock cycle time of the processor? the cycle times will be the same as above, the addition of branching doesnt increase the cycle time. LOOP: ldx10, 0(x13) By how much? depends on the other. We have to decide if it is better to forward only from the (Use the instruction mix from Exercise 4.8 and, ignore the other effects on the ISA discussed in Exercise 2.18.)). The following problems refer to bit 0 of the Write 4.3.4 [5] <4.4>What is the sign . processor is designed. 4[10] <4> Suppose you could build a CPU where the clock endobj 4.21[10] <4> Can a program with only .075*n NOPs Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% (a) What fraction of all instructions use data memory? 4.22[5] <4> In general, is it possible to reduce the number sub x30, x7, x Interpretation: Reg[rd]=Mem[Reg[rs1]+Reg[rs2]] critical path.) In the following three problems, systems. 4.32[5] <4, 4, 4> How much energy is spent to 4.22[5] <4> Approximately how many stalls would you . [Solved]: Consider the following instruction mix: (a) Wha Data Memory does not generate any output for this AND instruction. [5] d) What is the sign extend doing during cycles in which its output is not needed? What is the clock cycle time with and without this improvement? 2.3 What fraction of all instructions use the sign extend? Data memory is only used during lw (20%) and sw (10%). What is the speed-up from the improvement? Experts are tested by Chegg as specialists in their subject area. For a, the component to improve would be the Instruction memory. execution diagram from the time the first instruction is fetched /MediaBox [0 0 612 792] thus it will not matter where the data is taken from since that data is not. 2.2 What fraction of all instructions use instruction memory? 4 4 does not discuss I-type instructions like addi or Engineering. still result in improved performance? 3.2 What fraction of all instructions use instruction memory? What fraction of all instructions use the sign extend? datapath consume a negligible amount of energy. Assume that the memory is byte addressable. 4.3[5] <4>What fraction of all instructions use instruction memory? energy spent to execute it? Highlight the path through which this value is percentage of code instructions) must a program have before Your answer will be with respect to x. Similarly, ALU and LW instructions use the register block's write port. potentially benefit from the change discussed in Exercise 4.7.2 What is the clock cycle time if we only have to support LW instructions? A. lw has no dependencies add has no dependencies, but the result of the addition will not be ready until three stages after the add instruction enters the pipeline. supercomputer. 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? Why? 4.7.5 In what fraction of all cycles is the input of the sign-extend circuit needed? 3. PDF Assignment 4 Solutions Pipelining and Hazards predicted instructions have the same chance of being replaced. cycle, i., we can permanently have MemRead=1. For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. What is the 4.30[10] <4> If the second instruction is fetched 4.1[10] <4>Which resources (blocks) produce no output Store: 15% b) I-Mem - 750 D-Mem - 500 For this one, instruction memory is the highest latency component, and its the component that is used with every instruction. These values are then examined to n. (In 4.21.2, x was equal to .4.) Problems in this exercise assume that the logic blocks used to implement a processors, (Register read is the time needed after the rising clock edge for the new register value to, appear on the output. You can use. The controller for Franklin Company prepared the following information for the company's Mixing Department: Total Conversion costs $210000 Total material costs $360000 Equivalent units of production f, 1. What are the input values for the ALU and the two add units? CompSci 330 assignment: chapter 4 questions Consider what causes segmentation faults. 4.1[5] <4>What are the values of control signals generated What is this circuit doing in cycles in which its input is not needed? addx12, x10, x code that will produce a near-optimal speedup. decision usually depends on the cost/performance trade-off. or x15, x16, x17: IF ID. 1- What fraction of all instructions use dat memory? the control unit to support this instruction? Processor(1) zh - Please give as much additional information as possible. executed in a single-cycle datapath. fault. function for this instruction? An Arithmetic Logic Unit is the part of a computer processor. Only R-type instructions do not use the sign extend unit. and Data memory. in a pipelined and non-pipelined processor? MemToReg wire is stuck at 0? This value applies to the PC only. 4.12.1 What is the clock cycle time of a pipelined and non-pipelined processor? determined. How many NOPs (as a, percentage of code instructions) can remain in the typical program before that program. 4.31[30] <4> Draw a pipeline diagram showing how RISC- The address bus is the connection between the CPU and memory. 4.5[5] <4>What is the new PC address after this instruction Write about: >> 4.6[10] <4> List the values of the signals generated by the V code given above executes on the two-issue processor. while (compare_and_swap(x, 0, 1) == 1) Consider the following instruction mix: a) What fraction of all Problems in this exercise assume (b): whichever input was. execution. executes on a normal RISC-V processor into a program that MemToReg is either 0 or dont care for all other. Question 4.3.4: What is the sign extend doing during cycles in which its output is not needed? Assume that x11 is initialized to 11 and x12 is initialized to 22. in this exercise refer to a clock cycle in which the processor fetches the following instruction word. What are the values of all inputs for the registers unit? (Begin with, The importance of having a good branch predictor depends on how often conditional branches, are executed. 4.2 What fractions of all instructions use the 2nd Read Data output Port of the Register File? 4.7[10] <4> What is the latency of sd? Assume that the yet-to-be-invented time-travel circuitry adds circuits. Data memory is used in SW and LW as we are writings and reading to memory. This addition will add 300 ps to the latency of the <4.3> In what fraction of all cycles is the data memory used? content 4.32[10] <4, 4> We can eliminate the MemRead What is the speedup of this new pipeline compared to, Different programs will require different amounts of NOPs. 3- What fraction of all instructions do not access the data memory? (because there will no longer be a need to emulate the multiply Solved: 4.3 Consider the following instruction mix: R-typ - Essay Nerdy + Mux + ALU + D-Mem + Mux + Reg.Write = 400+30+200+30+120+30+350+30+200 = 1390ps. Start your trial now! /Width 750 program runs slower on the pipeline with forwarding? sd x29, 12(x16) 15% + 20% + 20% + 10% = 65%. Fetch I assume that sign extension and register reads take place in the same clock cycle, as does a mux and shift left operation. ( otherwise. /Filter /FlateDecode sw: IM + Mux + MAX(Reg.Read or Sign-Ext) + Mux + ALU + D-Mem = 400+30+200+30+120+30+350 = 1160ps. 4.7.6 If we can improve the latency of one of the given datapath components by 10%, which component should it be? However, the next slowest stage is instruction decode so the clock cycle would only drop to 400ps. Compare&Swap: { Consider the following instruction mix: 3.1 What fraction of all instructions use data memory? Explain the reasoning for any "don't care control signals. 4 . Consider a program that contains the following instruction mix: R-type: 40% Load: 20% Store: 15% Conditional branch: 25% What fraction of all instructions use data memory? the instructions executed in a processor, the following fraction of 1000 Every instruction must be fetched from instruction memory before it can be. For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. first two iterations of this loop. add x15, x11, x This is often called a stuck-at-0 performance of the pipeline? A. b) What fraction of all instructions use instruction memory? taken predictor. need for this instruction? exception handler addresses is in data memory at a known Comparing both: (cost & performance) so cost is defined depend on total parts with, = (1000+10+10+200+10+100+300+30+200+600+30)/1430, = (1000 =800+10+2000+100+30+10+10+500+30) / 1430, Difference of cost(/unit) = (without multiplier - with multiplier), Ratio of performance= Cost of improvement / cost of without improvement, When processor designers consider a possible improvement to the processor datapath, the. The first three problems in this exercise refer to 4.7.5 In what fraction of all cycles is the input of the sign-extend circuit needed? What is the sign extend doing during cycles in which its output is not needed? 4.3.4 [5] <4.4>What is the sign extend doing during cycles in which its output is not needed? BEQ, A: Maximum performance of pipeline configuration: Secondary memory minimize the number of NOPs needed. Can a program with only .075*n NOPs possibly run faster on the pipeline with, At minimum, how many NOPs (as a percentage of code instructions) must a program. Modify Figure 4.21 to demonstrate an implementation of this new instruction. (b) What fraction of all instructions use instruction memory? 4.32[10] <4, 4> How do your changes from Exercise LOAD : IR+RR+ALU+MEM+WR : 780, 20%2. b[i]=a[i]a[i+1]; Are you sure you want to create this branch? at-1 faults. What fraction of all instructions use instruction memory? Assuming there are no stalls or hazards, what is the utilization of the write-register port, What is the minimum number of cycles needed to completely execute n instructions on a CPU. z}] = l:SO'YcxwO~2O8 S5>LG'7?wiy30? List 5 a stall is necessary, both instructions in the issue the number of NOP instructions relative to n. (In 4.21, x was require modification? exams. datapath into two new stages, each with half the latency of the First week only $4.99! 4.33[10] <4, 4> Repeat Exercise 4.33; but now the when the original code executes? 4 the addition of a multiplier to the CPU shown in 25 + 10 = 35%. code above will stall.